Nonvolatile memory system with background reference positioning and local reference positioning
US10283215B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2017 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Jan 11, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory system, a nonvolatile memory controller and a method for reducing latency of a memory controller are disclosed. The nonvolatile memory system includes a read circuit that performs background reads of an indicator page of each block to identify outlier blocks. A background reference positioning circuit performs background reads of representative pages of the outlier block at threshold voltage offsets to identify sets of updated threshold voltage offset values. Upon endurance events, retention timer events and read disturb events at a closed block background reads are performed of representative pages of the closed block at threshold voltage offsets to identify sets of updated threshold voltage offset values. When a usage characteristic meets one or more usage characteristic threshold, the read circuit performs subsequent host-requested reads of pages of blocks meeting the usage characteristic threshold using a threshold voltage shift read instruction and using the corresponding set of updated threshold voltage offset values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.