Chip encapsulating method and chip encapsulating structure
US10283376B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | Apr 12, 2018 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Apr 12, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip encapsulating method includes: fixing a plurality of wafers to a first panel level substrate, the wafer including a plurality of chips; forming a re-distribution layer on the wafer for each of the chips; forming each individual chip and the re-distribution layer connected to the chip by cutting; fixing the chip and the re-distribution layer connected thereto to a second panel level substrate; and encapsulating the chip to form an encapsulating layer. A chip encapsulating structure is prepared by the above described chip encapsulating method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.