Pixel circuit
US10283559B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 3, 2017 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Jul 3, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/803
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A pixel arrangement includes a photodiode, a reset transistor configured to be controlled by a reset signal and coupled to a reset input voltage, a transfer gate transistor configured to transfer charge from the photodiode to a node, wherein the transfer gate transistor is controlled by a transfer gate voltage, and a source follower transistor controlled by the voltage on the node and coupled to a source follower voltage. A capacitor is coupled between the node and an input voltage. During a read operation the input voltage is increased to boost the voltage at the node. The increased input voltage may, for example, be one the reset input voltage, said source follower voltage, said transfer gate voltage and a boosting voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.