Voltage disconnect architecture
US10283982B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2016 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Aug 11, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02J7/00304
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A disconnect architecture for use with a system having a battery pack and positive and negative bus rails includes a mid-pack low-power (LP) relay, a fuse, semiconductor switches, and a sequencer circuit. The mid-pack LP relay is positioned between the rails at a mid-stack point of the battery pack, and divides a voltage across the battery pack when commanded open. The fuse is positioned between the mid-pack LP relay and the positive bus rail, and opens in response to a dead short condition of the system. The semiconductor switches are positioned in electrical parallel with the mid-pack LP relay. The sequencer circuit selectively turns on the semiconductor switches and thereby coordinates a flow of electrical current through the semiconductor switches and the mid-pack LP relay in response to a detected partial short condition of the system. A system includes the battery pack, bus rails, and disconnect architecture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.