Delay based comparator
US10284188B1 · kind B1 · utility
19Cited by
11References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2018 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Apr 4, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/48
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A comparator includes a pair of back-to-back negative-AND (NAND) gates and a delay circuit coupled to the pair of back-to-back NAND gates. The delay circuit is configured to modulate a triggering clock signal by an input voltage to generate a delayed clock signal with a delay that is based on the input voltage. Each of the pair of back-to-back NAND gates is configured to receive the delayed clock signal and generate a comparator output signal based on the delayed clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.