Semiconductor device
US10284192B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 22, 2018 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | May 22, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2017/0806
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device including a first control circuit, a memory and a second control circuit. The first control circuit includes a monitoring section which receives a voltage signal which includes a pulse signal having a plurality of different voltage levels superimposed on a power source voltage, monitors a level of the voltage signal and outputs a monitoring result, and a regulator which generates an internal voltage. The memory receives the internal voltage. The second control circuit receives the internal voltage, reproduces a clock and data from the pulse signal on the basis of the monitoring result, and performs trimming on the memory using the clock and the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.