Pure memristive logic gate
US10284203B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Jun 14, 2017 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Jun 14, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0069
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to an embodiment of the invention there is provided a device and method. The device may include a pure memristive logic gate, wherein the pure memristive logic gate consists essentially of at least one input memristive device and an output memristive device that is coupled to and differs from the at least one memristive device; wherein the pure memristive device is controlled by a single control voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.