Equalization circuit, a method of operating an equalization circuit and a system comprising an equalization circuit and an ADC
US10284220B1 · kind B1 · utility
0Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2018 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Sep 5, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/804
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present application relates to an EQ circuit, a method of operating it and a system comprising the EQ circuit and an ADC. The EQ circuit has a configurable load section, which is provided for selectively exposing one of a plurality of distinct loads to a reference source connected to a reference voltage signal input of the equalization circuit, and a logic section, which is arranged to accept a state signal from the ADC and to selectively connect one distinct load out of the plurality of distinct loads in response to the state signal. The state signal is indicative of an actual operation state of the ADC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.