Branch prediction suppression for blocks of instructions predicted to not include a branch instruction
US10289417B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2014 |
| Grant date | May 14, 2019 |
| Priority date | — |
| Expiry date | Oct 5, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing apparatus contains branch prediction circuitry including a micro branch target buffer, a full branch target buffer and a global history buffer. The branch target buffer entries contain history data which indicates whether or not a number of the following blocks of program instructions, subsequent to and sequential to a block of program instruction identified by that branch target buffer entry containing a branch instruction, do themselves contain any branch instructions. If the history data indicates that the following blocks of program instructions do not contain branches, then the operation of the branch prediction circuitry is suppressed for these following blocks of program instructions so as to save energy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.