Memory read-ahead using learned memory access patterns
US10289555B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2017 |
| Grant date | May 14, 2019 |
| Priority date | — |
| Expiry date | May 27, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and articles of manufacture comprising processor-readable storage media are provided to implement read-ahead memory operations using learned memory access patterns for memory management systems. For example, a method for managing memory includes receiving a request from requestor (e.g., an active process) to perform a memory access operation, which includes a requested memory address. A determination is made as to whether a data block (e.g., page) associated with the requested memory address resides in a cache memory. When the data block associated with the requested memory address is not in the cache memory, a memory read-ahead process is performed which includes identifying a learned memory access pattern associated with the requestor, wherein the learned memory access pattern includes a plurality of data blocks starting with the data block associated with the requested memory address, and prefetching the plurality of data blocks associated with the learned memory access pattern into the cache memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.