Generating hardware security logic
US10289873B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2016 |
| Grant date | May 14, 2019 |
| Priority date | — |
| Expiry date | Dec 23, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/032
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure includes systems and techniques relating to information flow and hardware security for digital devices and microprocessor systems. In general, in one implementation, a technique includes: receiving a hardware design specifying an implementation for information flow in a hardware configuration; receiving one or more labels annotating the hardware design; receiving a security property specifying a restriction relating to the one or more labels for implementing a secure information flow in the hardware configuration; designating each of the one or more labels to a corresponding security level in accordance with the specified restriction; and automatically assigning a respective value to each of the one or more labels in the hardware design, wherein each respective value is determined in accordance with the corresponding security level designated for each of the one or more labels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.