Integrated circuit fabrication with a passivation agent
US10290535B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2018 |
| Grant date | May 14, 2019 |
| Priority date | — |
| Expiry date | Mar 22, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76877
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Examples of fabricating an integrated circuit device are disclosed herein. In an embodiment, an integrated circuit workpiece is received that includes a conductive interconnect feature. A first Inter-Level Dielectric (ILD) layer is formed on the conductive interconnect feature, and a second ILD layer is formed on the first ILD layer. A hard mask is formed on the second ILD layer. A via recess is etched extending through the first ILD layer, the second ILD layer and the hard mask to expose the conductive interconnect feature. The etching includes providing a passivation agent that reacts with a material of the hard mask to reduce etchant sensitivity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.