BiCMOS integration with reduced masking steps
US10290630B2 · kind B2 · utility
1Cited by
8References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2015 |
| Grant date | May 14, 2019 |
| Priority date | — |
| Expiry date | Mar 17, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device is disclosed. The BiCMOS device includes a CMOS device in a CMOS region, a PNP bipolar device in a bipolar region, and an NPN bipolar device in the bipolar region. The NPN bipolar device has an extrinsic base being self-aligned with an emitter of the NPN bipolar device. The extrinsic base of the NPN bipolar device and an emitter of the PNP bipolar device share a P type dopant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.