Thin film transistor, array substrate and display panel having the same, and fabricating method thereof
US10290741B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | Nov 8, 2016 |
| Grant date | May 14, 2019 |
| Priority date | — |
| Expiry date | Nov 8, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02565
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present application discloses a thin film transistor including a base substrate and an active layer on the base substrate having a first portion corresponding to a channel region, a second portion corresponding to a source electrode contact region, and a third portion corresponding to a drain electrode contact region. The second portion and the third portion include a three-dimensional nanocomposite material having a semiconductor material matrix and a plurality of nanopillars in the semiconductor material matrix.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.