Packaging method and semiconductor device
US10290795B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2015 |
| Grant date | May 14, 2019 |
| Priority date | — |
| Expiry date | Nov 2, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/8506
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present disclosure provides a packaging method and a semiconductor device, the packaging method comprising: depositing a first sacrificial layer on a substrate to cover a semiconductor element formed on the substrate; covering a first dielectric layer on an upper surface and a side wall of the first sacrificial layer, the first dielectric layer has a first groove exposing part of the first sacrificial layer; covering a second sacrificial layer on surface of the exposed first sacrificial layer; covering a second dielectric layer on the second sacrificial layer and the exposed surface of the first dielectric layer, the second dielectric layer having a releasing hole exposing the second sacrificial layer and a second groove; depositing a filling layer to fill the second groove; by the releasing hole, removing the second sacrificial layer and the first sacrificial layer to form a cavity; depositing a third dielectric layer which covers the exposed surface of the second dielectric layer, and filling the releasing hole. According to the present application, a step of packaging using a conduit shell is removed, thereby reducing the packaging cost of the semiconductor element and impro…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.