Thin film transistor including recessed gate insulation layer and its manufacturing method, array substrate, and display device
US10290822B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2014 |
| Grant date | May 14, 2019 |
| Priority date | — |
| Expiry date | Nov 7, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K19/10
Abstract
A thin film transistor and its manufacturing method, an array substrate and a display device are disclosed, the thin film transistor is of a gate bottom contact type, and includes a gate electrode (3) and a gate insulation layer (2), the gate insulation layer (2) is provided with a recess (4) at a position corresponding to the gate electrode (3). With the thin film transistor, the problem of wire breakage in the active layer at the channel between the source/drain electrodes can be avoided, the performance and stability of the thin film transistor is improved, and the production cost is lowered down.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.