Feedforward phase noise compensation
US10291214B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2018 |
| Grant date | May 14, 2019 |
| Priority date | — |
| Expiry date | Feb 27, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Clock systems with phase noise compensation are provided herein. In certain implementations, a clock system includes a phase noise detector for detecting a phase noise of a clock signal, and an adjustable delay circuit for generating an adjusted clock signal based on delaying the clock signal with a controllable delay. Additionally, the phase noise detector generates an error signal indicated the phase noise of the clock signal, and controls the delay of the adjustable delay circuit with the error signal over time to thereby compensate the clock signal for phase noise. Thus, the adjusted clock signal has reduced phase noise compared to the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.