Referenceless clock and data recovery circuits
US10291241B2 · kind B2 · utility
2Cited by
3References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2018 |
| Grant date | May 14, 2019 |
| Priority date | — |
| Expiry date | Jun 14, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/20
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Referenceless clock and data recovery circuits are described that operate to align the clock/data strobe with each data eye to achieve a low bit error rate. The appropriate frequency and phase to be used is determined by an edge counter based frequency error detector and a phase error detector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.