Digital linearization technique for charge pump based fractional phased-locked loop
US10291243B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2018 |
| Grant date | May 14, 2019 |
| Priority date | — |
| Expiry date | Apr 23, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1976
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus includes an oscillator, a frequency divider, a phase circuit, a charge pump, and a filter. The frequency divider may generate an early feedback signal using a clock signal, and may assert a feedback signal a number of periods of the clock signal after asserting the early feedback signal. The phase circuit may generate a charge control signal using a reference clock signal and the feedback signal, and may generate a discharge control signal using the early feedback signal, the reference clock signal, and the feedback signal. The charge pump may charge or discharge a circuit node using the charge control signal and the discharge control signal to generate a frequency control signal. The filter circuit may attenuate at least one frequency component of the frequency control signal. The oscillator circuit may modify a frequency of the clock signal using the frequency control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.