Reception interface circuits supporting multiple communication standards and memory systems including the same
US10291275B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2017 |
| Grant date | May 14, 2019 |
| Priority date | — |
| Expiry date | Jul 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/90
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A reception interface circuit includes a termination circuit, a buffer and an interface controller. The termination circuit is configured to change a termination mode in response to a termination control signal. The buffer is configured to change a reception characteristic in response to a buffer control signal. The interface controller is configured to generate the termination control signal and the buffer control signal such that the reception characteristic of the buffer is changed in association with the change in the termination mode. The reception interface circuit may support various communication standards by changing the reception characteristic of the buffer in association with the termination mode. Using the reception interface circuit, communication efficiency of transceiver systems such as a memory system and/or compatibility between a transmitter device and a receiver device may be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.