Clock synchronization method, receiver, transmitter, and clock synchronization system
US10291446B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2018 |
| Grant date | May 14, 2019 |
| Priority date | — |
| Expiry date | Apr 27, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0048
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock synchronization method, a receiver, a transmitter, and a clock synchronization system, where the method includes obtaining a common reference clock signal, determining Bt according to the common reference clock signal and Mrd(t−1), where determining that Mrd(t−1) is a target Mrd when Ct obtained by means of calculation according to Mrd(t−1) is less than or equal to a threshold, where Ct=Bt−At, At is included in a residual time stamp (RTS) packet received by a receiver last time from the transmitter, and performing frequency division on the common reference clock signal using the target Mrd as a frequency dividing coefficient to obtain a first clock signal, and performing frequency multiplication processing on the first clock signal to obtain a service clock signal. Hence, random phase offset may be avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.