Techniques for hardware video encoding
US10291925B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2017 |
| Grant date | May 14, 2019 |
| Priority date | — |
| Expiry date | Sep 2, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/625
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An apparatus of video encoding is described herein. The apparatus includes an encoder and a hardware bit packing unit. The encoder includes a fixed function hierarchical motion estimation search unit, fixed function integer motion estimation search units, and a fixed function check and refinement unit. The check and refinement unit is to generate residuals using nested loops based on at least one spatial domain prediction and at least one frequency domain prediction and perform a final mode decision based on rate distortion optimization (RDO) costs associated with the generated residuals. The hardware bit packing unit is to pack bits as coded according to the final mode decision into a data format.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.