Patent · US Active

Semiconductor device and scan test method including writing and reading test data

US10295597B2 · kind B2 · utility

0Cited by

3References

15Claims

0Family size

Assignee

RENESAS ELECTRONICS CORPORATION · JP

Inventors

Yoichi Maeda · Somalomo, CM
Jun Matsushima · Tokyo, JP
Hiroki Wada · Yokohama, JP

Key dates

Filing date	Apr 16, 2015
Grant date	May 21, 2019
Priority date	—
Expiry date	Apr 16, 2035

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/267
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A semiconductor device includes a FIFO, a test data write circuit that sequentially writes a plurality of test data to the FIFO in synchronization with a first clock signal, and a test control circuit that, in parallel with writing of the plurality of test data to the FIFO by the test data write circuit, sequentially reads a plurality of test data stored in the FIFO in synchronization with a second clock signal that is not synchronous with the first clock signal and performs a scan test of a circuit to be tested.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.