Enhanced dynamic clock and voltage scaling (DCVS) scheme
US10296067B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2016 |
| Grant date | May 21, 2019 |
| Priority date | — |
| Expiry date | May 25, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In certain aspects, a method for frequency scaling comprises determining whether only a subset of multiple processors is active, wherein the multiple processors share one or more resources. The method also comprises increasing a frequency of at least one processor in the subset of the multiple processors if a determination is made that only the subset of the multiple processors is active and the frequency of the at least one processor is below a frequency threshold. This may be done, for example, to increase the time duration of an idle mode for the one or more shared resources and achieve an overall power reduction for a system including the multiple processors, the one or more shared resources, and/or other function blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.