System, apparatus and method for low overhead control transfer to alternate address space in a processor
US10296338B2 · kind B2 · utility
1Cited by
26References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2016 |
| Grant date | May 21, 2019 |
| Priority date | — |
| Expiry date | Feb 16, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3881
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a processor includes: an accelerator associated with a first address space; a core associated with a second address space and including an alternate address space configuration register to store configuration information to enable the core to execute instructions from the first address space; and a control logic to configure the core based in part on information in the alternate address space configuration register. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.