Parallelized execution of instruction sequences
US10296350B2 · kind B2 · utility
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65References
42Claims
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Key dates
| Filing date | Mar 31, 2015 |
| Grant date | May 21, 2019 |
| Priority date | — |
| Expiry date | Oct 4, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method which includes, in a processor that processes instructions of program code, processing one or more of the instructions by a first hardware thread. Upon detecting that an instruction defined as a parallelization point has been fetched for the first thread, a second hardware thread is invoked to process at least one of the instructions at least partially in parallel with processing of the instructions by the first hardware thread.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.