Nested quantum annealing correction
US10296352B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2017 |
| Grant date | May 21, 2019 |
| Priority date | — |
| Expiry date | Jun 15, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N10/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods of processing using a quantum processor are described. A method includes obtaining a problem Hamiltonian and defining a nested Hamiltonian with a plurality of logical qubits by embedding a logical KN representing the problem Hamiltonian into a larger KC×N, where N represents a number of the logical qubits and C represents a nesting level defining the amount of hardware resources for the nest Hamiltonian. The method also includes encoding the nested Hamiltonian into the plurality of physical qubits of the quantum processor; and performing a quantum annealing process with the quantum processor after the encoding.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.