Method for scheduling a processing device
US10296393B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2016 |
| Grant date | May 21, 2019 |
| Priority date | — |
| Expiry date | Apr 23, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hardware thread scheduler (HTS) is provided for a multiprocessor system. The HTS is configured to schedule processing of multiple threads of execution by resolving data dependencies between producer modules and consumer modules for each thread. Pattern adaptors may be provided in the scheduler that allows mixing of multiple data patterns across blocks of data. Transaction aggregators may be provided that allow re-using the same image data by multiple threads of execution while the image date remains in a given data buffer. Bandwidth control may be provided using programmable delays on initiation of thread execution. Failure and hang detection may be provided using multiple watchdog timers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.