Tile based interleaving and de-interleaving for digital signal processing
US10296456B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2013 |
| Grant date | May 21, 2019 |
| Priority date | — |
| Expiry date | Sep 10, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6505
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Tile based interleaving and de-interleaving of row-column interleaved data is described. In one example, the de-interleaving is divided into two memory transfer stages, the first from an on-chip memory to a DRAM and the second from the DRAM to an on-chip memory. Each stage operates on part of a row-column interleaved block of data and re-orders the data items, such that the output of the second stage comprises de-interleaved data. In the first stage, data items are read from the on-chip memory according to a non-linear sequence of memory read addresses and written to the DRAM. In the second stage, data items are read from the DRAM according to bursts of linear address sequences which make efficient use of the DRAM interface and written back to on-chip memory according to a non-linear sequence of memory write addresses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.