System and method for visualization in an electronic circuit design
US10296703B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2017 |
| Grant date | May 21, 2019 |
| Priority date | — |
| Expiry date | Sep 20, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a system and method for visualization of fixing of design rule violations in an electronic circuit design. Embodiments may include displaying at a graphical user interface at least a portion of an electronic design having at least one shape associated therewith and identifying one or more electronic design rules associated with the at least one shape. In response to identifying, embodiments may include determining a proposed shape based upon, at least in part, the one or more electronic design rules associated with the at least one shape, wherein the proposed shape is at least one of a trim shape, a bridge shape, and a patch shape and displaying the proposed shape at the graphical user interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.