System and method for multi-cycle write leveling
US10297310B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2016 |
| Grant date | May 21, 2019 |
| Priority date | — |
| Expiry date | Feb 24, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for multi cycle write leveling are disclosed. At least three data patterns are written into consecutive address locations of a memory device via corresponding write operations. Subsequently, predetermined beats of data strobe signals corresponding to certain predetermined write operations are gated. Based at least on the gating of predetermined data beats, a target data pattern to be read from the memory device is determined. Subsequently, a data read operation is performed, and the data written onto a specific address location of the memory device is read there from. The data thus read from the memory device is compared with the target pattern. Based on the comparison of the data read from the memory device with the target pattern, a delay cycle between the data strobe signals and clock signal is determined, and the data strobe signal and clock signal are accordingly calibrated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.