Systems and methods for memory protocol training
US10297311B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2018 |
| Grant date | May 21, 2019 |
| Priority date | — |
| Expiry date | Jan 30, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments provide for determining a delay of a data signal with respect to a data strobe signal within a memory system comprising a memory controller and a memory module. In particular, some embodiments adjust a phase between a data signal and a data strobe signal such that a data eye of the data signal arrives at a receiver latch of a memory module can be centered on a transition of the data strobe signal. By centering the data eye of the data signal with the transition of the data strobe signal, various embodiments can ensure that the data strobe signal transition falls between the leading and trailing edges of the data eye, which in turn permits the memory module to obtain correct data from the memory controller during a write operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.