Integrated circuit electrostatic discharge protection
US10298215B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2016 |
| Grant date | May 21, 2019 |
| Priority date | — |
| Expiry date | Nov 24, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/819
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Integrated circuits (ICs) include electrostatic discharge protection including a transistor having a drain operably coupled to a first rail of the integrated circuit and a source operatively coupled to a second rail of the integrated circuit. A voltage regulating trigger circuit is operatively coupled to the first rail and to a gate of the transistor to turn on of the transistor responsive to an ESD event affecting the integrated circuit, wherein the voltage regulating trigger circuit limits a potential of the first rail to a first potential and a gate potential of the transistor to a second potential, less than the first potential but sufficient to turn the transistor on to conduct current arising from the ESD event from the first rail to the second rail.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.