Method of arranging capacitor array of successive approximation register analog-to-digital converter
US10298254B1 · kind B1 · utility
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Key dates
| Filing date | Aug 28, 2018 |
| Grant date | May 21, 2019 |
| Priority date | — |
| Expiry date | Aug 28, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/804
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of arranging a capacitor array of a successive approximation register analog-to-digital converter in a successive approximation process, the method including: splitting a binary capacitor array into unit capacitors, then sorting, grouping, and rotating the original binary capacitive array involved in successive approximation conversion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.