Delay circuit for a radio signal with filter circuitry to linearize a phase shift of an output signal relative to an input
US10298278B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 5, 2017 |
| Grant date | May 21, 2019 |
| Priority date | — |
| Expiry date | Jun 5, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H7/255
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A delay circuit for time offsetting an input radiofrequency signal, includes an all-pass filter having a given central frequency to linearize a phase-shift of an output signal relative to the input signal as a function of the frequency on a first frequency range; and first and second antiresonant circuits having respectively first and second central frequencies, the all-pass filter and the antiresonant circuits configured to linearize the phase-shift of the output signal relative to the input signal as a function of the frequency on a second frequency range including the first range. The difference between first and second central frequencies is less than 30% of the value of one of both frequencies, the difference between the first central frequency and the given central frequency of the all-pass filter is less than 30% of the value of a highest frequency between the first central frequency and the given central frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.