Multiphase clock data recovery with adaptive tracking for a multi-wire, multi-phase interface
US10298381B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2018 |
| Grant date | May 21, 2019 |
| Priority date | — |
| Expiry date | Apr 30, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4923
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Data communication apparatus and methods for a multi-wire interface are disclosed. A half rate clock and data recovery (CDR) circuit derives a clock signal including pulses corresponding to symbols transmitted on a 3-wire interface, where the symbols are transmitted at a particular frequency with each of the symbols occurring over a unit interval (UI) time period. The first clock signal is input to a flip-flop logic included in a delay loop, and serves to trigger the first flip-flop logic. A second clock signal is generated using a programmable generator in the delay loop and has a frequency of a half UI and is fed back to a data input of the flip-flop. The output of the flip-flop is used as a recovered clock signal for the CDR at a half rate frequency. This design provides ease of timing control, a delay line without extra nonlinear-effects, and less hardware overhead.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.