Vector permutation circuit and vector processor
US10303473B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2016 |
| Grant date | May 28, 2019 |
| Priority date | — |
| Expiry date | Mar 29, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A vector permutation circuit and a vector processor are provided. The vector permutation circuit includes a grouping unit, m selection units connected to the grouping unit, j switching units connected to the m selection units, and a control unit connected to each selection unit and each switching unit, where each switching unit is connected to m/j selection units; the grouping unit divides to-be-permutated vector data into n vector data groups and output the n vector data groups to the m selection units; under control of the control unit, each selection unit selects a second vector data group from an input first vector data group, and outputs the second vector data group to a switching unit connected to the selection unit; under control of the control unit, each switching unit switches and outputs elements in the input second vector data group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.