Arbitrating and multiplexing circuitry
US10303624B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2016 |
| Grant date | May 28, 2019 |
| Priority date | — |
| Expiry date | May 5, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Arbitrating and multiplexing circuitry for performing an arbitration between a plurality of inputs and a selection of at least one of said plurality of inputs to provide an output comprises arbitrating tree circuitry having X arbitrating levels, where X is an integer greater than one; and multiplexing tree circuitry having Y multiplexing levels, where Y is an integer greater than one; wherein (i) said Y multiplexing levels comprise a first set of said multiplexing levels upstream of a second set of said multiplexing levels; (ii) said first set of said multiplexing levels is configured to operate in parallel with at least some of said X arbitrating levels, whereby said first set of multiplexing levels is configured to perform a partial selection in parallel with said arbitration performed by said X arbitrating levels; and (iii) said second set of said multiplexing levels is configured to operate in series with said X arbitrating levels, whereby said second set of multiplexing levels completes said selection to provide said output following completion of and in dependence upon said arbitration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.