Hardware queue manager with water marking
US10303627B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2017 |
| Grant date | May 28, 2019 |
| Priority date | — |
| Expiry date | Nov 2, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for managing one or more queues in a multi-processor environment includes a memory configured to be accessed by a plurality of processing elements, and a queue manager disposed in communication with a plurality of processors and with the memory, the queue manager configured to control a queue in the memory, the queue including a plurality of queue elements, the queue manager configured to intercept a message from a processing element of the plurality of processing elements and perform one or more queuing operations on the queue based on the message. The system also includes a dynamically configurable queue full value maintained by the queue manager, the queue full value being a threshold value that specifies a maximum number of the queue elements that can be written to before a queue full condition is detected, the maximum number based on a number of processing elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.