Operating system transparent system memory abandonment
US10304418B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2016 |
| Grant date | May 28, 2019 |
| Priority date | — |
| Expiry date | Jan 26, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/121
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An electronic processing system may include a processor and a multi-level memory coupled to the processor, the multi-level memory including at least a main memory and a fast memory, the fast memory having relatively faster performance as compared to the main memory. The system may further include a fast memory controller coupled to the fast memory and a graphics controller coupled to the fast memory controller. The fast memory may include a cache portion allocated to a cache region to allow a corresponding mapping of elements of the main memory in the cache region, and a graphics portion allocated to a graphics region for the graphics controller with no corresponding mapping of the graphics region with the main memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.