High signal voltage tolerance in single-ended memory interface
US10304520B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2018 |
| Grant date | May 28, 2019 |
| Priority date | — |
| Expiry date | Feb 2, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4074
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a line-termination circuit and a continuous-time linear equalizer circuit. The line-termination circuit may be configured to generate a data signal in response to an input signal. The input signal generally resides in a first voltage domain. The input signal may be single-ended. The data signal may be generated in the first voltage domain. The continuous-time linear equalizer circuit may be configured to generate an intermediate signal by equalizing the data signal relative to a reference voltage. The continuous-time linear equalizer circuit generally operates in a second voltage domain. The first voltage domain may be higher than the second voltage domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.