SRAM architecture

US10304525B2 · kind B2 · utility

Assignee

• XENERGIC AB · SE

Inventors

• Babak Mohammadi · Lund, SE
• Joachim Neves Rodrigues · Lund, SE

Key dates

• Filing date: Sep 17, 2015
• Grant date: May 28, 2019
• Expiry date: Sep 17, 2035

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C8/08
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

The present invention relates generally to the field of semiconductor memories and in particular to memory cells comprising a static random access memory (SRAM) bitcell (100). Leakage current in the read path is reduced by connecting a read access transistor terminal either to GND or VDD during read access or write access and idle state. The SKAM cell inverters may be asymmetrical in size. The memory may comp rise various boost circuits to allow low voltage operation or application of distinguished supply voltages.