Fan-out semiconductor package
US10304784B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2018 |
| Grant date | May 28, 2019 |
| Priority date | — |
| Expiry date | Mar 28, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fan-out semiconductor package includes a wiring portion, semiconductor chips, a dummy chip, and an encapsulant. The wiring portion includes an insulating layer, conductive patterns formed on the insulating layer, and conductive vias penetrating through the insulating layer and connected to the conductive patterns. The semiconductor chips are disposed on one region of the wiring portion, and the dummy chip is disposed on another region thereof and has a thickness smaller than those of the semiconductor chips. The encapsulant encapsulates at least portions of the semiconductor chips and the dummy chip. An upper surface of the wiring portion is disposed below a center line of the fan-out semiconductor package, and the thickness t of the dummy chip is such that T/2≤t≤3T/2 in which T is a distance from the upper surface of the wiring portion to the center line of the fan-out semiconductor package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.