Protective layers for high-yield printed electronic devices
US10304836B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2018 |
| Grant date | May 28, 2019 |
| Priority date | — |
| Expiry date | Jul 22, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10159
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Printed electronic devices are provided. In embodiments, such a device comprises a plurality of contact pads arranged in a pattern; a plurality of electrode traces arranged in another pattern, the plurality of electrode traces comprising a set of bottom electrode traces and a set of top electrode traces, each electrode trace in electrical communication with an associated contact pad of the plurality of contact pads; a plurality of memory cells, each memory cell located at an intersection of a pair of electrode traces of the plurality of electrode traces and comprising a bottom electrode layer formed from a region of one of the bottom electrode traces, a top electrode layer formed from a region of one of the top electrode traces, and a ferroelectric layer between the bottom and top electrode layers; and a protective layer covering the plurality of electrode traces, the protective layer formed from a curable composition comprising an amine modified polyester (meth)acrylate, a (meth)acrylated amine oligomer, a (meth)acrylate monomer, a clay mineral, and a photoinitiator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.