Array substrate and method of forming the same
US10304860B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2016 |
| Grant date | May 28, 2019 |
| Priority date | — |
| Expiry date | Oct 28, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/13685
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate includes a substrate, a buffer layer, a first shielding pattern, a passivation layer, a first semiconductor pattern, a gate insulating layer, a first gate pattern, an interlayer insulating layer, and two first source/drain electrode patterns. A first through hole and a second through hole are arranged on the array substrate. One of the first source/drain electrode patterns is electrically connected to the first semiconductor pattern and the first shielding pattern through the first through hole. The other one of the first source/drain electrode patterns is electrically connected to the first semiconductor pattern through the second through hole and is insulated from the first shielding pattern. The present invention where the array substrate and the method of forming the array substrate are proposed is related to a top-gate design. The driving ability of the TFT driving circuit still improves without increasing the original processes and production costs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.