Integration of graphene and boron nitride hetero-structure device over semiconductor layer
US10304967B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2018 |
| Grant date | May 28, 2019 |
| Priority date | — |
| Expiry date | Mar 2, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0254
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microelectronic device includes a gated graphene component over a semiconductor material. The gated graphene component includes a graphitic layer having at least one layer of graphene. The graphitic layer has a channel region, a first connection and a second connection make electrical connections to the graphitic layer adjacent to the channel region. The graphitic layer is isolated from the semiconductor material. A backgate region having a first conductivity type is disposed in the semiconductor material under the channel region. A first contact field region and a second contact field region are disposed in the semiconductor material under the first connection and the second connection, respectively. At least one of the first contact field region and the second contact field region has a second, opposite, conductivity type. A method of forming the gated graphene component in the microelectronic device with a transistor is disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.