Anti-short-circuit integrated chip and terminal facility
US10305277B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2018 |
| Grant date | May 28, 2019 |
| Priority date | — |
| Expiry date | Mar 29, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01H2085/0486
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The disclosure provides an anti-short-circuit integrated chip and terminal facility. The integrated chip comprises: a control unit having a first output terminal configured for outputting a first signal and a second output terminal configured for outputting a second signal; and an insurance apparatus having a first insurance part connected to the first output terminal and a second insurance part connected to the second output terminal. The insurance parts are configured for limiting the currents flowed through the insurance parts when the currents flowed through the insurance parts exceed the current threshold. The chip device can be protected from being damaged when there is short circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.