Low voltage input calibrating digital to analog converter
US10305361B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2017 |
| Grant date | May 28, 2019 |
| Priority date | — |
| Expiry date | Sep 20, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/66
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A calibrating digital to analog converter (calDAC) architecture uses a low voltage memory to store the digital inputs of calDACs. The calDAC architecture includes a low voltage domain and a high voltage domain coupled to the low voltage domain. The low voltage domain includes a calDAC memory and a finite state machine (FSM). The high voltage domain includes a calDAC core, an interface circuit, and a bias control circuit coupled to the interface circuit. The interface circuit may be provided between the calDAC core and the low voltage domain. The bias control circuit is coupled to the interface circuit to generate a bias voltage for the interface circuit to drive switch transistors of the calDAC core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.