Patent · US Active

Fault attack protection against synchronized fault injections

US10305479B1 · kind B1 · utility

3Cited by

7References

19Claims

0Family size

Assignee

NXP B.V. · NL

Inventors

Stefan Doll · Obermoschel, DE
Markus Regner · Munich, DE
Sandeep Jain · Milpitas, US

Key dates

Filing date	Jun 12, 2018
Grant date	May 28, 2019
Priority date	—
Expiry date	Jun 12, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH03K2005/00019
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Various embodiments relate to a circuit, including: a first secure circuit configured to receive an input and to produce a first output; a first delay circuit configured to receive the first output and to produce a first delayed output delayed by a time N; a second delay circuit configured to receive the input and to produce a delayed input delayed by a time N; a second secure circuit configured to receive the delayed input and to produce a second delayed output; and a comparator configured to compare the first delayed output to the second delayed output and to produce a result, wherein the result is one of the first delayed output or second delayed output when the first delayed output matches the second delayed output and the result is an error value when the first delayed output does not match the second delayed output.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.