Patent · US Active

Delay locked loop including a delay code generator

US10305494B2 · kind B2 · utility

2Cited by

10References

13Claims

0Family size

Assignee

SAMSUNG ELECTRONICS CO., LTD. · KR

Inventors

Hoon Lee · Yongin-si, KR
Donghun Lee · Daejeon, KR
Jaewon Lee · Gangneung-si, KR

Key dates

Filing date	May 18, 2017
Grant date	May 28, 2019
Priority date	—
Expiry date	Jun 13, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH03K2005/00234
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A delay locked loop includes a delay line, a delay circuit, a phase detector, a delay code generator, and a delay controller. The delay line may delay an input clock signal in units of unit delay in response to a delay control code to generate an output clock signal. The delay circuit may delay the output clock signal to generate a delay clock signal. The phase detector may compare the input clock signal and the delay clock signal to generate a phase detection signal. The delay code generator may compare the input clock signal and the delay clock signal to detect a phase difference therebetween, and generate a delay code using the phase difference. The delay controller may generate the delay control code using the delay code and the phase detection signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.